For those FPGA chips which lack of internal storage resource and the metastability problem that the data transferred between the different clock domains. A method was designed to acquire the video image data based on FPGA+DSP framework. Under the effect of IIC configuration module and de-interleave module, by through desiring 3 lower depth asynchronous FIFO realized video-data stream’s transfer between the different clock domain, the data written into FIFO at send clock domain and read at received clock domain, it realized the data transfer and acquire simultaneously. By analysis the utilization of the FPGA chip resource and carry on a system test, the result of test have shown that the system can accurately re-appear the input video image and realize the real time video data acquisition.