Aiming at the problem of large-capacity data, need memory cache in high-speed real-time image processing system, a new SDRAM controller based on FPGA was proposed. Based on the analysis of the basic operation principle of SDRAM, through introducing the state machine and arbitration mechanism, the purpose of high-speed data cache and transmission is realized by carrying on the design input and simulation validation in QuartusII development environments using Verilog language. This paper introduces the specific design of each module and the realization of the whole design in detail. The test results show that the controller designed is flexible, stable, reliable, low cost, and can be used as IP core in different SOC high-speed cache system.